The present invention generally relates to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a trench power MOSFET.
MOSFET has gradually replaced the bipolar joint transistor (BJT). The MOSFET is one of the most popular integrated circuits (ICs) due to the power-saving ability and the rapid switching frequency of the MOSFET. In particular, the basic operation theorem of the trench power MOSFET is same as that of other kinds of MOSFET and the trench power MOSFET has a higher turn-on current of up to several amperes (A). Additionally, the trench power MOSFET is able to be advantageously operated by a low controlling voltage and has a lower power-consumption.
FIGS. 1-5 show a conventional method of fabricating trench power MOSFET. In FIG. 1, a silicon substrate 50 is provided and is used as a drain region of the MOSFET. A plurality of trenches 52 is then formed in the silicon substrate 50. In FIG. 2, a gate oxide layer 54 is formed in the sidewall of the trenches 52 and a polysilicon layer 56 is also filled within the trenches 52. The polysilicon layer 56 is stripped away and the silicon substrate 50 is exposed, and the polysilicon layer 56 which remains in the trenches 52 is used as a gate region.
In FIG. 3, a photoresist layer 58 is deposited on the silicon substrate 50 and a portion of silicon substrate 50 between two trenches 52 is covered for patterning. The portion called a base region 68 is defined as source region 66. Afterwards, a heating tube process is implemented to form a source region 66. The photoresist layer 58 on the silicon substrate 50 is stripped away in FIG. 4. Finally, in FIG. 5, a dielectric layer 60 and metal interconnect 62 are deposited to form a conventional trench power MOSFET.
During the above process of the MOSFET, a photoresist layer 58 is required to cover the base region 68 for forming a source region 66. However, with the shrinkage of the devices, a photomask problem often occurs during a step of photomask alignment. Therefore, the degree of difficulty of the base region formation is severely increased, resulting in a low yield rate for the process. Moreover, the electrical characteristic of the base region 68 is neutralized when a drive-in step of the base region 68 is performed. As a result, the electrical characteristic between the metal interconnect 62 and the source region 66 degrades to reduce the performance of the trench power MOSFET.
One object of the present invention is a method of fabricating trench power MOSFET in which a gate mask layer is used to overlap the gate region. An aligned source region is formed by the mask layer between the two gate regions to save an additional photomask of forming the source region.
Another object of the present invention is a method of fabricating trench power MOSFET in which a mask layer capping the gate region is utilized to form the aligned source region and to solve the alignment problem of the photomask in the source region.
According to the above objects, the present invention sets forth a method of fabricating trench power MOSFET. An epitaxial silicon layer is formed on a substrate and the epitaxial silicon layer serves as a drain region. A device region is then formed in the epitaxial silicon layer. A first implanting step is performed on the device region to form a first doped region. A second implanting step is then performed on the first doped region of the device region to form a second doped region in the first doped region. Afterwards, a first patterned etching is employed to form a plurality of trenches in the device region wherein a depth of the trenches is greater than that of the first doped region. A gate oxide layer and a polysilicon layer are sequentially formed on the second doped region to fill the trenches and to define a gate region.
A second patterned etching is performed to form a gate mask layer and to cover the gate oxide layer and the polysilicon layer of the trenches, in which a portion of the second doped region between the trenches is exposed and defines a base region, and a width of the gate mask layer is greater than that of the base region. The mask region layer is stripped away to expose the polysilicon layer in the trenches. A portion of the polysilicon layer is etched by a blanket etching step to expose the gate oxide layer and simultaneously the base region is etched to expose the first doped region to create an aligned source region. The source region is positioned between the base region and the gate region.
Significantly, the polysilicon layer of the gate region is etched and the gate oxide layer is used as an etching stop layer. The polysilicon layer remains in the trenches as the gate region. More importantly, if the polysilicon layer of the gate region is etched, the second doped region of the base region is simultaneously etched until the first doped region is exposed. In other words, the second doped region between two trenches is divided into two portions by the base region and each portion is a source region. A contact region is finally constructed in the source region and a metallization step is performed to connect the contact region by a conductive layer, thus forming a trench power MOSFET.
The width of the source region and the base region have been reduced by the smaller size of the device since the width of the gate mask layer is advantageously greater than that of the base region in the present invention. A gate mask layer is formed by covering the trenches with gate oxide and the polysilicon layer by using a mask layer to save an additional mask for fabricating the source region. Specifically, better electrical contact is established between the source region and the conductive layer. There is advantageously an electrical increment between the source region and the conductive layer in the present invention due to an electrical contact between the upper surface of the source region and the conductive layer and a contact interface between the source region and the base region.
In summary, the present invention utilizes a method of fabricating trench power MOSFET. A mask layer overlaps with the gate region. An aligned source region is formed by the mask layer between the two gate regions to save an additional photomask for forming the source region. Further, the mask layer capping the gate region is utilized to form the aligned source region and to solve the alignment problem of the photomask in the source region.